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| bq4832Y RTC Module With 32Kx8 NVSRAM Features (R) Integrated SRAM, real-time clock, CPU supervisor, crystal, power-fail circuit, and battery (R) Real-Time Clock counts hundredths of seconds through years in BCD format (R) RAM-like clock access (R) Compatible with industrystandard 32K x 8 SRAMs (R) Unlimited write cycles (R) 10-year minimum data retention and clock operation in the absence of power (R) Automatic power-fail chip deselect and write-protection (R) Watchdog timer, power-on reset, alarm/periodic interrupt, powerfail and battery-low warning (R) Software clock calibration for greater than 1 minute per month accuracy General Description The bq4832Y RTC Module is a nonvolatile 262,144-bit SRAM organized as 32,768 words by 8 bits with an integral real-time clock and CPU supervisor. The CPU supervisor provides a programmable watchdog timer and a microprocessor reset. O t he r f e a tu re s i n cl u d e a l a rm, power-fail, and periodic interrupts, and a battery-low warning. The device combines an internal lithium battery, quartz crystal, clock and power-fail chip, and a full CMOS SRAM in a plastic 32-pin DIP module. The RTC Module directly replaces industry-standard SRAMs and also fits into many EPR O M a n d E E P R O M s o ck e ts without any requirement for special write timing or limitations on the number of write cycles. Registers for the real-time clock, alarm and other special functions are located in registers 7FF0h- 7FFFh of the memory array. The clock and alarm registers are dual-port read/write SRAM locations that are updated once per second by a clock control circuit from the internal clock counters. The dual-port registers allow clock updates to occur without interrupting normal access to the rest of the SRAM array. The bq4832Y also contains a powerfail-detect circuit. The circuit deselects the device whenever VCC falls below tolerance, providing a high degree of data security. The battery is electrically isolated when shipped from the factory to provide maximum battery capacity. The battery remains disconnected until the first application of VCC. Pin Connections RST NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC NC INT WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Pin Names A0-A14 CE RST WE OE DQ0-DQ7 INT VCC VSS Address input Chip enable Microprocessor reset Write enable Output enable Data in/data out Programmable interrupt +5 volts Ground 32-Pin DIP Module PN483201.eps Sept. 1996 C 1 bq4832Y Functional Description Figure 1 is a block diagram of the bq4832Y. The following sections describe the bq4832Y functional operation, including memory and clock interface, data-retention modes, power-on reset timing, watchdog timer activation, and interrupt generation. Figure 1. Block Diagram Truth Table VCC < VCC (max.) CE VIH VIL > VCC (min.) VIL VIL < VPFD (min.) > VSO VSO X X OE X X VIL VIH X X WE X VIL VIH VIH X X Mode Deselect Write Read Read Deselect Deselect DQ High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery-backup mode Sept. 1996 C 2 bq4832Y Address Map The bq4832Y provides 16 bytes of clock and control status registers and 32,752 bytes of storage RAM. Figure 2 illustrates the address map for the bq4832Y. Table 1 is a map of the bq4832Y registers, and Table 2 describes the register bits. CE and OE control the state of the eight three-state data I/O signals. If the outputs are activated before tAA, the data lines are driven to an indeterminate state until tAA. If the address inputs are changed while CE and OE remain low, output data remains valid for tOH (output data hold time), but goes indeterminate until the next address access. Write Mode The bq4832Y is in write mode whenever WE and CE are active. The start of a write is referenced from the latter-occurring falling edge of WE or CE. A write is terminated by the earlier rising edge of WE or CE. The addresses must be held valid throughout the cycle. CE or WE must return high for a minimum of tWR2 from CE or tWR1 from WE prior to the initiation of another read or write cycle. Data-in must be valid tDW prior to the end of write and remain valid for tDH1 or tDH2 afterward. OE should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on CE and OE, a low on WE disables the outputs tWZ after WE falls. Memory Interface Read Mode The bq4832Y is in read mode whenever OE (output enable) is low and CE (chip enable) is low. The device architecture allows ripple-through access of data from eight of 262,144 locations in the static storage array. Thus, the unique address specified by the 15 address inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data is available at the data I/O pins within tAA (address access time) after the last address input signal is stable, providing that the CE and OE (output enable) access times are also satisfied. If the CE and OE access times are not met, valid data is available after the latter of chip enable access time (tACE) or output enable access time (tOE). 16 Bytes Clock and Control Status Registers 7FFF 7FF0 7FEF 32,752 Bytes Storage RAM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Year Month Date Days Hours Minutes Seconds Control Watchdog Interrupts Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Tenths/ Hundredths Flags 7FFF 7FFE 7FFD 7FFC 7FFB 7FFA 7FF9 7FF8 7FF7 7FF6 7FF5 7FF4 7FF3 7FF2 7FF1 7FF0 0000 15 FG483201.eps Figure 2. Address Map Sept. 1996 C 3 bq4832Y Data-Retention Mode With valid VCC applied, the bq4832Y operates as a conventional static RAM. Should the supply voltage decay, the RAM automatically power-fail deselects, write-protecting itself tWPT after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "don't care." If power-fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within time t WPT, writeprotection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source, which preserves data. The internal coin cell maintains data in the bq4832Y after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and Vcc rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write-protection continues for tCER after VCC reaches VPFD to allow for processor stabilization. After tCER, normal RAM operation can resume. Clock Interface Reading the Clock The interface to the clock and control registers of the bq4832Y is the same as that for the general-purpose storage memory. Once every second, the user-accessible clock/calendar locations are updated simultaneously from the internal real time counters. To prevent reading data in transition, updates to the bq4832Y clock registers should be halted. Updating is halted by setting the read bit D6 of the control register to 1. As long as the read bit is 1, updates to user-accessible clock locations are inhibited. Once the frozen clock information is retrieved by reading the appropriate clock memory locations, the read bit should be reset to 0 in order to allow updates to occur from the internal counters. Because the internal counters are not halted by setting the read bit, reading the clock locations has no effect on clock accuracy. Once the read bit is reset to 0, within one second the internal registers update the user-accessible registers with the correct time. A halt command issued during a clock update allows the update to occur before freezing the data. Table 1. bq4832Y Clock and Control Register Map Address 7FFF 7FFE 7FFD 7FFC 7FFB 7FFA 7FF9 7FF8 7FF7 7FF6 7FF5 7FF4 7FF3 7FF2 7FF1 7FF0 Notes: D7 X X X X X OSC W WDS AIE ALM3 ALM2 ALM1 ALM0 WDF D6 D5 D4 10 Years X X 10 Month X 10 Date FTE X X X 10 Hours 10 Minutes 10 Seconds R S BM4 BM3 BM2 PWRIE ABE PIE X 10-date alarm X 10-hour alarm Alarm 10 minutes Alarm 10 seconds 0.1 seconds AF PWRF BLF D2 D1 Year Month Date X Day Hours Minutes Seconds Calibration BM1 BM0 WD1 RS3 RS2 RS1 Alarm date Alarm hours Alarm minutes Alarm seconds 0.01 seconds PF X X D3 D0 Range (h) 00-99 01-12 01-31 01-07 00-23 00-59 00-59 00-31 Register Year Month Date Days Hours Minutes Seconds Control Watchdog Interrupts Alarm date Alarm hours Alarm minutes Alarm seconds 0.1/0.01 seconds Flags WD0 RS0 01-31 00-23 00-59 00-59 00-99 X X = Unused bits; can be written and read. Clock/Calendar data in 24-hour BCD format. BLF = 1 for low battery. OSC = 1 stops the clock oscillator. Interrupt enables are cleared on power-up. Sept. 1996 C 4 bq4832Y Table 2. Clock and Control Register Bits Bits ABE AF AIE ALM0-ALM3 BLF BM0-BM4 FTE OSC PF PIE PWRF PWRIE R RS0-RS3 S W WD0-WD1 WDF WDS Description Alarm interrupt enable in battery-backup mode Alarm interrupt flag Alarm interrupt enable Alarm repeat rate Battery-low flag Watchdog multiplier Frequency test mode enable Oscillator stop Periodic interrupt flag Periodic interrupt enable Power-fail interrupt flag Power-fail interrupt enable Read clock enable Periodic interrupt rate Calibration sign Write clock enable Watchdog resolution Watchdog flag Watchdog steering Calibrating the Clock The bq4832Y real-time clock is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The quartz crystal is contained within the bq4832Y package along with the battery. The clock accuracy of the bq4832Y module is tested to be within 20ppm or about 1 minute per month at 25C. The oscillation rates of crystals change with temperature as Figure 3 shows. To compensate for the frequency shift, the bq4832Y offers onboard software clock calibration. The user can adjust the calibration based on the typical operating temperature of individual applications. The software calibration bits are located in the control register. Bits D0-D4 control the magnitude of correction, and bit D5 the direction (positive or negative) of correction. Assuming that the oscillator is running at exactly 32,786 Hz, each calibration step of D0-D4 adjusts the clock rate by +4.068 ppm (+10.7 seconds per month) or -2.034 ppm (-5.35 seconds per month) depending on the value of the sign bit D5. When the sign bit is 1, positive adjustment occurs; a 0 activates negative adjustment. The total range of clock calibration is +5.5 or -2.75 minutes per month. Two methods can be used to ascertain how much calibration a given bq4832Y may require in a system. The first involves simply setting the clock, letting it run for a month, and then comparing the time to an accurate known reference like WWV radio broadcasts. Based on the variation to the standard, the end user can adjust the clock to match the system's environment even after the product is packaged in a non-serviceable enclosure. The only requirement is a utility that allows the end user to access the calibration bits in the control register. Setting the Clock Bit D7 of the control register is the write bit. Like the read bit, the write bit when set to a 1 halts updates to the clock/calendar memory locations. Once frozen, the locations can be written with the desired information in 24-hour BCD format. Resetting the write bit to 0 causes the written values to be transferred to the internal clock counters and allows updates to the user-accessible registers to resume within one second. Use the write bit, D7, only when updating the time registers (7FFF-7FF9). Stopping and Starting the Clock Oscillator The OSC bit in the seconds register turns the clock on or off. If the bq4832Y is to spend a significant period of time in storage, the clock oscillator can be turned off to preserve battery capacity. OSC set to 1 stops the clock oscillator. When OSC is reset to 0, the clock oscillator is turned on and clock updates to user-accessible memory locations occur within one second. The OSC bit is set to 1 when shipped from the Benchmarq factory. Sept. 1996 C Figure 3. Frequency Error 5 bq4832Y The second approach uses a bq4832Y test mode. When the frequency test mode enable bit FTE in the days register is set to a 1, and the oscillator is running at exactly 32,768 Hz, the LSB of the seconds register toggles at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz indicates a (1E6*0.01024)/512 or +20 ppm oscillator frequency error, requiring ten steps of negative calibration (10*-2.034 or -20.34) or 001010 to be loaded into the calibration byte for correction. To read the test frequency, the bq4832Y must be selected and held in an extended read of the seconds register, location 7FF9, without having the read bit set. The frequency appears on DQ0. The FTE bit must be set using the write bit control. The FTE bit must be reset to 0 for normal clock operation to resume. ally, when the watchdog times out, the watchdog flag bit (WDF) in the flags register, location 7FF0, is set. To reset the watchdog timer, the microprocessor must write to the watchdog register. After being reset by a write, the watchdog time-out period starts over. As a precaution, the watchdog circuit is disabled on a power failure. The user must, therefore, set the watchdog at boot-up for activation. Interrupts The bq4832Y allows four individually selected interrupt events to generate an interrupt request on the INT pin. These four interrupt events are: n The watchdog timer interrupt, programmable to occur according to the time-out period and conditions described in the watchdog timer section. n The periodic interrupt, programmable to occur once every 122s to 500ms. n The alarm interrupt, programmable to occur once per second to once per month. n The power-fail interrupt, which can be enabled to be asserted when the bq4832Y detects a power failure. The periodic, alarm, and power-fail interrupts are enabled by an individual interrupt-enable bit in register 7FF6, the interrupts register. When an event occurs, its event flag bit in the flags register, location 7FF0, is set. If the corresponding event enable bit is also set, then an interrupt request is generated. Reading the flags register clears all flag bits and makes INT high impedance. To reset the flag register, the bq4832Y addresses must be held stable at location 7FF0 for at least 50ns to avoid inadvertent resets. Power-On Reset The bq4832Y provides a power-on reset, which pulls the RST pin low on power-down and remains low on powerup for tCER after VCC passes VPFD. Watchdog Timer The watchdog circuit monitors the microprocessor's activity. If the processor does not reset the watchdog timer within the programmed time-out period, the circuit asserts the INT or RST pin. The watchdog timer is activated by writing the desired time-out period into the eight-bit watchdog register described in Table 3 (device address 7FF7). The five bits (BM4-BM0) store a binary multiplier, and the two lower-order bits (WD1-WD0) select the resolution, where 00 = 1 16 second, 01 = 1 4 second, 10 = 1 second, and 11 = 4 seconds. The time-out period is the multiplication of the five-bit multiplier with the two-bit resolution. For example, writing 00011 in BM4-BM0 and 10 in WD1-WD0 results in a total time-out setting of 3 x 1 or 3 seconds. A multiplier of zero disables the watchdog circuit. Bit 7 of the watchdog register (WDS) is the watchdog steering bit. When WDS is set to a 1 and a time-out occurs, the watchdog asserts a reset pulse for tCER on the RST pin. During the reset pulse, the watchdog register is cleared to all zeros disabling the watchdog. When WDS is set to a 0, the watchdog asserts the INT pin on a time-out. The INT pin remains low until the watchdog is reset by the microprocessor or a power failure occurs. Addition- Periodic Interrupt Bits RS3-RS0 in the interrupts register program the rate for the periodic interrupt. The user can interpret the interrupt in two ways: either by polling the flags register for PF assertion or by setting PIE so that INT goes active when the bq4832Y sets the periodic flag. Reading the flags register resets the PF bit and returns INT to the high-impedance state. Table 4 shows the periodic rates. Table 3. Watchdog Register Bits MSB 7 WDS 6 BM4 5 BM3 4 BM2 Bits 3 BM1 2 BM0 1 WD1 LSB 0 WD0 Sept. 1996 C 6 bq4832Y Table 4. Periodic Rates RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interrupt Rate None 10ms 100ms 122.07s 244.14s 488.281s 976.5625 1.953125ms 3.90625ms 7.8125ms 15.625ms 31.25ms 62.5ms 125ms 250ms 500ms The alarm interrupt can be made active while the bq4832Y is in the battery-backup mode by setting ABE in the interrupts register. Normally, the INT pin tristates during battery backup. With ABE set, however, INT is driven low if an alarm condition occurs and the AIE bit is set. Because the AIE bit is reset during power-on reset, an alarm generated during power-on reset updates only the flags register. The user can read the flags register during boot-up to determine if an alarm was generated during power-on reset. 1 0 0 0 1 1 0 0 Table 5. Alarm Frequency (Alarm Bits DQ7 of Alarm Registers) ALM3 1 1 ALM2 1 1 ALM1 1 1 ALM0 1 0 Alarm Frequency Once per second Once per minute when seconds match Once per hour when minutes, and seconds match Once per day when hours, minutes, and seconds match When date, hours, minutes, and seconds match 0 0 0 0 Power-Fail Interrupt When V CC falls to the power-fail-detect point, the power-fail flag PWRF is set. If the power-fail interrupt enable bit (PWRIE) is also set, then INT is asserted low. The power-fail interrupt occurs tWPT before the bq4832Y generates a reset and deselects. The PWRIE bit is cleared on power-up. Alarm Interrupt Registers 7FF5-7FF2 program the real-time clock alarm. During each update cycle, the bq4832Y compares the date, hours, minutes, and seconds in the clock registers with the corresponding alarm registers. If a match between all the corresponding bytes is found, the alarm flag AF in the flags register is set. If the alarm interrupt is enabled with AIE, an interrupt request is generated on INT. The alarm condition is cleared by a read to the flags register. ALM3-ALM0 puts the alarm into a periodic mode of operation. Table 5 describes the selectable rates. Battery-Low Warning The bq4832Y checks the internal battery on power-up. If the battery voltage is below 2.2V, the battery-low flag BLF in the flags register is set to a 1 indicating that clock and RAM data may be invalid. Sept. 1996 C 7 bq4832Y Absolute Maximum Ratings Symbol VCC VT TOPR TSTG TBIAS TSOLDER Note: Parameter DC voltage applied on VCC relative to VSS DC voltage applied on any pin excluding VCC relative to VSS Operating temperature Storage temperature (VCC off; oscillator off) Temperature under bias Soldering temperature Value -0.3 to 7.0 -0.3 to 7.0 0 to +70 -40 to +70 -10 to +70 +260 Unit V V C C C C For 10 seconds VT VCC + 0.3 Conditions Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. Recommended DC Operating Conditions (TA = TOPR) Symbol VCC VSS VIL VIH Note: Parameter Supply voltage Supply voltage Input low voltage Input high voltage Minimum 4.5 0 -0.3 2.2 Typical 5.0 0 Maximum 5.5 0 0.8 VCC + 0.3 Unit V V V V Notes Typical values indicate operation at TA = 25C. Sept. 1996 C 8 bq4832Y DC Electrical Characteristics (TA = TOPR, VCCmin Symbol ILI ILO VOH VOL IOD ISB1 ISB2 Parameter Input leakage current Output leakage current Output high voltage Output low voltage RST, INT sink current Standby supply current Standby supply current Minimum 2.4 10 Typical 3 2 VCC VCCmax) Unit A A V V mA mA mA Conditions/Notes VIN = VSS to VCC CE = VIH or OE = VIH or WE = VIL IOH = -1.0 mA IOL = 2.1 mA VOL = 0.4V CE = VIH CE VCC - 0.2V, 0V VIN 0.2V, or VIN VCC - 0.2V Min. cycle, duty = 100%, CE = VIL, II/O = 0mA Maximum 1 1 0.4 6 4 ICC VPFD VSO Notes: Operating supply current Power-fail-detect voltage Supply switch-over voltage 4.30 - 55 4.37 3 75 4.50 - mA V V Typical values indicate operation at TA = 25C, VCC = 5V. RST and INT are open-drain outputs. Capacitance (TA = 25C, F = 1MHz, VCC = 5.0V) Symbol CI/O CIN Note: Parameter Input/output capacitance Input capacitance Minimum Typical Maximum 10 10 Unit pF pF Conditions Output voltage = 0V Input voltage = 0V These parameters are sampled and not 100% tested. Sept. 1996 C 9 bq4832Y AC Test Conditions Parameter Input pulse levels Input rise and fall times Input and output timing reference levels Output load (including scope and jig) Test Conditions 0V to 3.0V 5 ns 1.5 V (unless otherwise specified) See Figures 4 and 5 Figure 4. Output Load A Figure 5. Output Load B Read Cycle Symbol tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH (TA = TOPR, VCCmin VCC VCCmax) -85 Parameter Min. 85 5 0 0 0 10 Max. 85 85 45 35 25 Unit ns ns ns ns ns ns ns ns ns Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A Sept. 1996 C Conditions Read cycle time Address access time Chip enable access time Output enable to output valid Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output in high Z Output hold from address change 10 bq4832Y Read Cycle No. 1 (Address Access) 1,2 Read Cycle No. 2 (CE Access) 1,3,4 Read Cycle No. 3 (OE Access) 1,5 Notes: 1. WE is held high for a read cycle. 2. Device is continuously selected: CE = OE = VIL. 3. Address is valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Device is continuously selected: CE = VIL. Sept. 1996 C 11 bq4832Y Write Cycle Symbol tWC tCW tAW tAS tWP tWR1 tWR2 tDW tDH1 tDH2 tWZ tOW Notes: (TA =TOPR , VCCmin VCC VCCmax) -85 Parameter Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write Min. 85 75 75 0 65 5 15 35 0 10 0 0 Max. 30 Units ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) Measured from address valid to beginning of write. (2) Measured from beginning of write to end of write. (1) Measured from WE going high to end of write cycle. (3) Measured from CE going high to end of write cycle. (3) Measured to first low-to-high transition of either CE or WE. Measured from WE going high to end of write cycle. (4) Measured from CE going high to end of write cycle. (4) I/O pins are in output state. (5) I/O pins are in output state. (5) Conditions/Notes 1. A write ends at the earlier transition of CE going high and WE going high. 2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low. 3. Either tWR1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state. Sept. 1996 C 12 bq4832Y Write Cycle No. 1 (WE-Controlled) 1,2,3 Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5 Notes: 1. CE or WE must be high during address transition. 2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If OE is high, the I/O pins remain in a state of high impedance. 4. Either tWR1 or tWR2 must be met. 5. Either tDH1 or tDH2 must be met. Sept. 1996 C 13 bq4832Y Power-Down/Power-Up Cycle (TA = TOPR) Symbol tPF tFS tPU tCER tDR tWPT Notes: Parameter VCC slew, 4.50 to 4.20 V VCC slew, 4.20 to VSO VCC slew, VSO to VPFD (max.) Chip enable recovery time Data-retention time in absence of VCC Write-protect time Minimum 300 10 0 40 10 40 Typical 100 100 Maximum 200 160 Unit s s s ms years s Time during which SRAM is write-protected after VCC passes VFPD on power-up. TA = 25C. (2) Delay after VCC slews down past VPFD before SRAM is write-protected. Conditions 1. Typical values indicate operation at TA = 25C, VCC = 5V. 2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the accumulated time in absence of power beginning when power is first applied to the device. Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Power-Down/Power-Up Timing Notes: 1. PWRIE is set to "1" to enable power fail interrupt. 2. RST and INT are open drain and require an external pull-up resistor. Sept. 1996 C 14 bq4832Y Data Sheet Revision History Change No. 1 2 2 Notes: Page No. 4 4 9 Description Corrected the locations of bits D6 and D4 of the Interrupts Register and the corresponding bits D5 and D3 of the Flags Register (these were reversed). Corrected the alarm date register (7FF5) to allow for 01-31 days in a month instead of 01-07 days. Lowered ISB1 from 4, 7mA to 3, 6mA; lowered ISB2 typical from 2.5mA to 2mA. Change 1 = Mar. 1996 B changes from Oct. 1995 A. Change 2 = Sept. 1996 C changes from Mar. 1996 B. Sept. 1996 C 15 bq4832Y MA: 32-Pin A-Type Module 32-Pin MA (A-Type Module) Inches Dimension A A1 B C D E e G L S Min. 0.365 0.015 0.017 0.008 1.670 0.710 0.590 0.090 0.120 0.075 Max. 0.375 0.023 0.013 1.700 0.740 0.630 0.110 0.150 0.110 Millimeters Min. 9.27 0.38 0.43 0.20 42.42 18.03 14.99 2.29 3.05 1.91 Max. 9.53 0.58 0.33 43.18 18.80 16.00 2.79 3.81 2.79 Sept. 1996 C 16 bq4832Y Ordering Information bq4832Y MA Speed Options: 85 = 85 ns Package Option: MA = A-type module Device: bq4832Y 32K x 8 Real-Time Clock Module Sept. 1996 C 17 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated WWW..COM Copyright (c) Each Manufacturing Company. All Datasheets cannot be modified without permission. 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